A Simulation Testbench For Predicting Nonlinearity in ADC Arrays

13 February, 2024

In our last two blog posts, we explored sources of low-light nonlinearity (INL) in CMOS sensors, along with some solutions to reduce the disturbances. To test these approaches, we’ve developed a simulation methodology to predict the low-light INL in an ADC array. 

First, we modeled the ADC array and plotted the INL. We also modeled the routing resistance for all the supplies, grounds, biases and ramp in the simulation testbench. The references — ramp and biases — are routed horizontally, while the supplies and grounds are routed horizontally and vertically.  

We modeled the ADC array by dividing it into sections and using m-factor, taking special care that any supply/ground-related variation can be simulated in a reasonable runtime. We also included dark columns in the testbench. The ADCs are RC extracted so we can see the effect of parasitic capacitance in the results. We also carefully modeled vertical routing for the supplies and ground to represent actual routing in the sensor.  

We set up the testbench so that a section of the array is kept at a fixed dark signal level. The input to the remainder of the ADCs in the array is swept to their INL plot. We compared the linearity of each fixed dark section to determine if there is any spatial pattern. 

The image below shows the simulation results before and after modifications, with the INL plot for the first 25% of the signal range.



The original result displays the INL plot without modifications, and the next two plots show the INL with the modifications we mentioned in our last blog post. In one plot, the comparator bias is not sampled, while in the other case the comparator bias is sampled. As we can see, the INL improves significantly when sampling the comparator bias.

To learn more, read our new white paper.