• Large and small SPAD pixel arrays
  • Quench logic, AFE, OR tree to combine large SPAD output
  • Histogram at 800MHz
  • ~40k frames per second
  • 1.1/1.2/2.5/7.0/25.0 volt supplies
  • 5.6Gbps CML serial interface
  • 3-D Stacked SPAD process
    • Top layer: SPAD array in 65nm
    • Bottom layer: logic chip in 40nm