Exploring Sources of Low-light Nonlinearity in CMOS Sensors
In a single-slope architecture, analog to digital converters (ADCs) have some shared common nets, including supplies, grounds, biases and ramp. A larger number of ADCs converting at the same time can cause kickback on these shared nets, leading to nonidealities — one of which is integrated nonlinearity (INL).
This effect is more prominent in the dark signal region where the pixel’s temporal noise and ADC dominate photon shot noise. The ADCs, converting a brighter signal level, have more shot noise and don’t convert at the same time, resulting in a more distributed kickback. In addition to optically black columns, the number of ADCs converting in the dark signal region can change depending on the scene. This disturbance also has a spatial component; the ADCs close to the source of the disturbance experience larger kickback, resulting in larger INL. This INL, which is scene-dependent in both magnitude and spatial distribution, is very difficult to correct in post-processing, making it desirable to reduce the INL on the chip.
Source 1: Ramp
The first major source of INL is ramp. Due to the disturbance in ramp slope, the ADCs converting the active array will have bumps in their INL plot at low-light levels. The magnitude of the disturbance is lower in ADCs farther from the source, as it gets low pass filtered from the RC parasitic on the ramp distribution routing.
The kickback effect from the preamp output transition — via parasitic capacitance to ramp — causes the disturbance on the ramp. Due to small ADC pitch, tighter routing is required, making it more difficult to isolate the ramp. Depending on the scene, if the percentage of aggressors increases, kickback will also increase. When creating a layout for the ADC column, it is therefore important to consider the ramp routing.
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Another source of parasitic coupling is the gate-to-drain capacitance (CGD) of the input MOSFET of the preamp. These devices are designed to have a large W and L to reduce flicker noise and have a larger associated capacitance. Using a cascode configuration on the preamp helps to reduce the Miller effect of the capacitance.
Source 2: Comparator Bias
Another source of disturbance is the comparator bias. The disturbance — which can be on the bias itself or on the supply/ ground to which it is referenced — is caused by the CGD of the current source — i.e., the same mechanism as preamp.
The supply/ground disturbance is caused by sudden IR drop when the comparator output switches. Since the current is not negligible, the IR drop level can become large — especially when many ADCs convert simultaneously or when impedance of supply and ground is large, for example, due to the limited number of metal layers.
Due to current trends to move to higher resolution in the same image sensor format and a higher frame rate, ADC pitch is decreasing to fit more ADCs and achieve the specification. But because the size of the sensor is not also being adjusted, the routing for the supply and ground nets has not improved by the same factor. The IR drop causes a change in the VGS of the comparator bias, changing the current for the victim ADCs comparator. In turn, noise on the bias current alters the transition time of the comparator — and manifest as nonlinearity.
Reducing the Effects of Nonlinearity
Nonlinearity becomes more significant for faster ADC count rates, which reduce effective row time to achieve high frame rates. To reduce the disturbance, we have multiple options:
- First, we can increase the drive strength of the bias generator to decrease the impedance of the bias node, which will help settle the disturbance faster.
- Second, we can decrease the number of fast-switching gates on the same power domain, reducing the IR drop on the supply/ground. We can accomplish this by moving these devices to a different power domain. We must also take care to minimize supply/ground routing resistance.
- Another approach is to reduce the effect of the glitch on the victim ADCs by sampling the bias voltage in each ADC separately. As a result, the disturbance will not propagate through the bias net; any disturbance on the supply/ground will be mirrored on the sampled bias voltage, maintaining the same VGS. It’s important to take proper care to size the sampling cap so the supply/ground disturbance doesn’t change the VGS.